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30 v zero-drift, rail-to-rail output precision amplifier data sheet ada4638-1 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features single supply operation: 4.5 v to 30 v dual supply operation: 2.25 v to 15 v low offset voltage: 4 v maximum input offset voltage drift: 0.05 v/c maximum high gain: 130 db minimum high psrr: 120 db minimum high cmrr: 130 db minimum input common-mode range includes lower supply rail rail-to-rail output low supply current: 0.95 ma maximum applications electronic weigh scale pressure and position sensors strain gage amplifiers medical instrumentation thermocouple amplifiers pin configurations nc 1 ? in 2 +in 3 v? 4 nc 8 v+ 7 out 6 nc 5 notes 1. nc = no connect. do not connect to this pin. a da4638-1 top view (not to scale) 10072-001 figure 1. 8-lead soic 10072-002 ada4638-1 top view (not to scale) notes 1. nc = no connect. do not connect to this pin. 2. it is recommended that the exposed pad be connected to v?. 3 +in 4 v? 1 nc 2 ?in 6out 5nc 8nc 7v+ figure 2. 8-lead lfcsp general description the ada4638-1 is a high voltage, high precision, zero-drift amplifier featuring rail-to-rail output swing. it is guaranteed to operate from 4.5 v to 30 v single supply or 2.25 v to 15 v dual supplies while consuming less than 0.95 ma of supply current at 5 v. with an offset voltage of 4 v, offset drift less than 0.05 v/c, no 1/f noise, and input voltage noise of only 1.2 v p-p (0.1 hz to 10 hz), the ada4638-1 is suited for high precision applications where large error sources cannot be tolerated. pressure sensors, medical equipment, and strain gage amplifiers benefit greatly from nearly zero drift over the wide operating temperature range. many applications can take advantage of the rail-to-rail output swing provided by the ada4638-1 to maximize the signal- to-noise ratio (snr). the ada4638-1 is specified for the extended industrial (?40c to +125c) temperature range and is available in 8-lead lfcsp (3 mm 3 mm) and soic packages. table 1. analog devices, inc., zero-drift op amp portfolio operating voltage type product offset voltage (v) max offset voltage drift (v/c) max 30 v single ada4638-1 4.5 0.08 single ad8638 9 0.06 16 v dual ad8639 9 0.06 ada4528-1 2.5 0.015 AD8628 5 0.02 ad8538 13 0.1 single ada4051-1 15 0.1 ad8629 5 0.02 ad8539 13 0.1 dual ada4051-2 15 0.1 5 v quad ad8630 5 0.02
ada4638-1 data sheet rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? pin configurations ........................................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? electrical characteristics30 v operation ............................. 3 ? electrical characteristics10 v operation ............................. 4 ? electrical characteristics5 v operation................................ 5 ? absolute maximum ratings............................................................ 6 ? thermal resistance ...................................................................... 6 ? esd caution.................................................................................. 6 ? typical performance characteristics ..............................................7 ? applications information .............................................................. 16 ? differentiation ............................................................................ 16 ? theory of operation .................................................................. 17 ? input protection ......................................................................... 17 ? no output phase reversal ........................................................ 17 ? noise considerations................................................................. 18 ? comparator operation.............................................................. 18 ? precision low-side current shunt sensor.............................. 20 ? printed circuit board layout ................................................... 20 ? outline dimensions ....................................................................... 21 ? ordering guide .......................................................................... 21 ? revision history 10/11revision 0: initial version
data sheet ada4638-1 rev. 0 | page 3 of 24 specifications electrical characteristics30 v operation v s = 30 v, v cm = v sy /2 v, t a = 25c, unless otherwise specified. table 2. parameter symbol test conditions/comments min typ max unit input characteristics offset voltage v os 0.5 4.5 v ?40c t a +125c; soic 12.5 v ?40c t a +125c; lfcsp 14.5 v offset voltage drift v os /t ?40c t a +125c; soic 0.08 v/c ?40c t a +125c; lfcsp 0.1 v/c input bias current i b 45 90 pa ?40c t a +125c 500 pa input offset current i os 25 105 pa ?40c t a +125c 170 pa input voltage range 0 27 v common-mode rejection ratio cmrr v cm = 0 v to 27 v 130 142 db ?40c t a +125c 130 db open-loop gain a vo r l = 10 k, v o = 1 v to 29 v 140 165 db ?40c t a +125c 140 db input resistance, common mode r incm 330 g input capacitance, differential mode c indm 4 pf input capacitance, common mode c incm 9 pf output characteristics output voltage high v oh r l = 10 k to v cm 29.90 29.92 v ?40c t a +125c 29.85 v r l = 2 k to v cm 29.50 29.58 v ?40c t a +125c 29.35 v output voltage low v ol r l = 10 k to v cm 50 60 mv ?40c t a +125c 95 mv r l = 2 k to v cm 235 270 mv ?40c t a +125c 445 mv short-circuit current i sc 38 ma closed-loop output impedance z out f = 1 mhz, a v = +1 220 power supply power supply rejection ratio psrr v s = 4.5 v to 30 v 120 143 db ?40c t a +125c 120 db supply current/amplifier i sy i o = 0 ma 0.85 1.05 ma ?40c t a +125c 1.25 ma dynamic performance slew rate sr r l = 10 k, c l = 20 pf, a v = +1 1.5 v/s overload recovery time r l = 10 k, c l = 20 pf, a v = ?100 8 s settling time to 0.1% t s v in = 5 v step, r l = 10 k, c l = 20 pf, a v = ?1 4 s unity-gain crossover ugc v in = 30 mv p-p, r l = 10 k, c l = 20 pf, a v = +1 1.3 mhz phase margin m v in = 30 mv p-p, r l = 10 k, c l = 20 pf, a v = +1 69 degrees gain-bandwidth product gbp v in = 30 mv p-p, r l = 10 k, c l = 20 pf, a v = +100 1.5 mhz ?3 db closed-loop bandwidth f ?3db v in = 30 mv p-p, r l = 10 k, c l = 20 pf, a v = +1 2.5 mhz noise performance voltage noise e n p-p f = 0.1 hz to 10 hz 1.2 v p-p voltage noise density e n f = 1 khz 66 nv/hz current noise density i n f = 1 khz 0.1 pa/hz
ada4638-1 data sheet rev. 0 | page 4 of 24 electrical characteristics10 v operation v s = 10 v, v cm = v sy /2 v, t a = 25c, unless otherwise specified. table 3. parameter symbol test conditions/comments min typ max unit input characteristics offset voltage v os 0.1 4 v ?40c t a +125c; soic 9 v ?40c t a +125c; lfcsp 12 v offset voltage drift v os /t ?40c t a +125c; soic 0.05 v/c ?40c t a +125c; lfcsp 0.08 v/c input bias current i b 20 50 pa ?40c t a +125c 250 pa input offset current i os 20 80 pa ?40c t a +125c 140 pa input voltage range 0 7 v common-mode rejection ratio cmrr v cm = 0 v to 7 v 130 155 db ?40c t a +125c 130 db open-loop gain a vo r l = 10 k, v o = 1 v to 9 v 130 160 db ?40c t a +125c 130 db input resistance, common mode r incm 250 g input capacitance, differential mode c indm 4 pf input capacitance, common mode c incm 9 pf output characteristics output voltage high v oh r l = 10 k to v cm 9.96 9.97 v ?40c t a +125c 9.95 v r l = 2 k to v cm 9.85 9.86 v ?40c t a +125c 9.75 v output voltage low v ol r l = 10 k to v cm 20 25 mv ?40c t a +125c 40 mv r l = 2 k to v cm 80 90 mv ?40c t a +125c 145 mv short-circuit current i sc 22 ma closed-loop output impedance z out f = 1 mhz, a v = +1 300 power supply power supply rejection ratio psrr v s = 4.5 v to 30 v 120 143 db ?40c t a +125c 120 db supply current/amplifier i sy i o = 0 ma 0.8 0.95 ma ?40c t a +125c 1.15 ma dynamic performance slew rate sr r l = 10 k, c l = 20 pf, a v = +1 1.5 v/s overload recovery time r l = 10 k, c l = 20 pf, a v = ?100 14 s settling time to 0.1% t s v in = 2 v step, r l = 10 k, c l = 20 pf, a v = ?1 3 s unity-gain crossover ugc v in = 30 mv p-p, r l = 10 k, c l = 20 pf, a v = +1 1.1 mhz phase margin m v in = 30 mv p-p, r l = 10 k, c l = 20 pf, a v = +1 67 degrees gain bandwidth product gbp v in = 30 mv p-p, r l = 10 k, c l = 20 pf, a v = +100 1.4 mhz ?3 db closed-loop bandwidth f ?3db v in = 30 mv p-p, r l = 10 k, c l = 20 pf, a v = +1 1.9 mhz noise performance voltage noise e n p-p f = 0.1 hz to 10 hz 1.2 v p-p voltage noise density e n f = 1 khz 66 nv/hz current noise density i n f = 1 khz 0.1 pa/hz
data sheet ada4638-1 rev. 0 | page 5 of 24 electrical characteristics5 v operation v s = 5 v, v cm = v sy /2 v, t a = 25c, unless otherwise specified. table 4. parameter symbol test conditions/comments min typ max unit input characteristics offset voltage v os 1 13 v ?40c t a +125c; soic 18 v ?40c t a +125c; lfcsp 21 v offset voltage drift v os /t ?40c t a +125c; soic 0.05 v/c ?40c t a +125c; lfcsp 0.08 v/c input bias current i b 30 90 pa ?40c t a +125c 230 pa input offset current i os 60 170 pa ?40c t a +125c 200 pa input voltage range 0 3 v common-mode rejection ratio cmrr v cm = 0 v to 3 v 118 140 db ?40c t a +125c 118 db open-loop gain a vo r l = 10 k, v o = 0.5 v to +4.5 v 125 150 db ?40c t a +125c 125 db input resistance, common mode r incm 75 g input capacitance, differential mode c indm 4 pf input capacitance, common mode c incm 9 pf output characteristics output voltage high v oh r l = 10 k to v cm 4.98 4.984 v ?40c t a +125c 4.97 v r l = 2 k to v cm 4.90 4.92 v ?40c t a +125c 4.87 v output voltage low v ol r l = 10 k to v cm 7.5 10 mv ?40c t a +125c 15 mv r l = 2 k to v cm 37 45 mv ?40c t a +125c 70 mv short-circuit current i sc 22 ma closed-loop output impedance z out f = 1 mhz, a v = +1 340 power supply power supply rejection ratio psrr v s = 4.5 v to 30 v 120 143 db ?40c t a +125c 120 db supply current/amplifier i sy i o = 0 ma 0.8 0.95 ma ?40c t a +125c 1.15 ma dynamic performance slew rate sr r l = 10 k, c l = 20 pf, a v = +1 1.5 v/s overload recovery time r l = 10 k, c l = 20 pf, a v = ?100 22 s settling time to 0.1% t s v in = 1 v step, r l = 10 k, c l = 20 pf, a v = ?1 3 s unity-gain crossover ugc v in = 20 mv p-p, r l = 10 k, c l = 20 pf, a v = +1 1.0 mhz phase margin m v in = 20 mv p-p, r l = 10 k, c l = 20 pf, a v = +1 64 degrees gain bandwidth product gbp v in = 20 mv p-p, r l = 10 k, c l = 20 pf, a v = +100 1.3 mhz ?3 db closed-loop bandwidth f ?3db v in = 20 mv p-p, r l = 10 k, c l = 20 pf, a v = +1 1.8 mhz noise performance voltage noise e n p-p f = 0.1 hz to 10 hz 1.2 v p-p voltage noise density e n f = 1 khz 70 nv/hz current noise density i n f = 1 khz 0.015 pa/hz
ada4638-1 data sheet rev. 0 | page 6 of 24 absolute maximum ratings thermal resistance table 5. parameter rating supply voltage 33 v input voltage 1 v sy input current 10 ma differential input voltage v sy output short-circuit duration to gnd indefinite storage temperature range ?65c to +150c operating temperature range ?40c to +125c junction temperature range ?65c to +150c lead temperature (soldering, 60 sec) 300c ja is specified for a device soldered on a 4-layer jedec standard board with zero airflow. for lfcsp packages, the exposed pad is soldered to the board. table 6. thermal resistance package type ja jc unit 8-lead soic 120 45 c/w 8-lead lfcsp 75 12 c/w esd caution 1 input voltage should always be limited to less than 30 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
data sheet ada4638-1 rev. 0 | page 7 of 24 typical performance characteristics t a = 25c, unless otherwise noted. 0 2 4 6 8 10 12 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 8 9 10 number of amplifiers offset voltage (v) v sy = 2.5v v cm =v sy /2 150 units 10072-003 figure 3. input offset voltage distribution 0 2 4 6 8 10 12 14 16 18 20 0 0.010.020.030.040.050.060.070.08 number of amplifiers tcv os (v/c) 10072-004 v sy = 2.5v v cm =v sy /2 ?40c < t a < +125c 140 lfcsp units figure 4. input offset voltage drift distribution 0 5 10 15 20 25 30 0 0.010.020.030.040.050.060.070.08 number of amplifiers tcv os (v/c) v sy = 2.5v v cm =v sy /2 ?40c t a +125c 140 soic units 10072-105 figure 5. input offset voltage drift distribution 0 5 10 15 20 25 30 ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 number of amplifiers offset voltage (v) v sy = 15v v cm =v sy /2 150 units 10072-006 figure 6. input offset voltage distribution 0 2 4 6 8 10 12 14 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 number of amplifiers tcv os (v/c) v sy = 15v v cm =v sy /2 ?40c < t a < +125c 140 lfcsp units 10072-007 figure 7. input offset voltage drift distribution 0 2 4 6 8 10 12 14 16 18 0 0.010.020.030.040.050.060.070.08 number of amplifiers tcv os (v/c) 10072-108 v sy =15v v cm =v sy /2 ?40c t a +125c 140 soic units figure 8. input offset voltage drift distribution
ada4638-1 data sheet rev. 0 | page 8 of 24 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 offset vol t age (v) common-mode voltage (v) v sy = 2.5v 10072-005 figure 9. input offset voltage vs. common-mode voltage ?150 ?100 ?50 0 50 100 150 200 ?50 ?25 0 25 50 75 100 125 input bias current (pa) temperature (c) i b + i b ? v sy = 2.5v 10072-009 figure 10. input bias current vs. temperature ?150 ?100 ?50 0 50 100 150 0 0.5 1.0 1.5 2.0 2.5 3.0 input bias current (pa) common-mode voltage (v) i b + i b ? 10072-010 v sy = 2.5v figure 11. input bias current vs. common-mode voltage ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 offset voltage (v) common-mode voltage (v) v sy =15v 10072-008 figure 12. input offset voltage vs. common-mode voltage ?250 ?200 ?150 ?100 ?50 0 50 100 150 ?50 ?25 0 25 50 75 100 125 input bias current (pa) temperature (c) i b + i b ? v sy = 15v 10072-012 figure 13. input bias current vs. temperature ?150 ?100 ?50 0 50 100 150 input bias current (pa) common-mode voltage (v) i b + i b ? 10072-013 v sy =15v 0 3 6 9 121518212427 figure 14. input bias current vs. common-mode voltage
data sheet ada4638-1 rev. 0 | page 9 of 24 0.01m 0.1m 1m 0.01 0.1 1 10 0.001 0.01 0.1 1 10 100 output vol t age (v ol ) to supply rail (v) load current (ma) ?40c +25c +85c +125c v sy = 2.5v 10072-011 figure 15. output voltage (v ol ) to supply rail vs. load current 0.01m 0.1m 1m 0.01 0.1 1 10 0.001 0.01 0.1 1 10 100 output voltage (v oh ) to supply rail (v) load current (ma) ?40c +25c +85c +125c v sy = 2.5v 10072-015 figure 16. output voltage (v oh ) to supply rail vs. load current 0 10 20 30 40 50 60 70 ?50 ?25 0 25 50 75 100 125 output voltage (v ol ) to supply rail (mv) temperature (c) r l = 2k ? r l = 10k ? r l = 100k ? v sy = 2.5v 10072-016 figure 17. output voltage (v ol ) to supply rail vs. temperature 0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 output voltage (v ol ) to supply rail (v) load current (ma) ?40c +25c +85c +125c 10072-014 v sy = 15v figure 18. output voltage (v ol ) to supply rail vs. load current 1m 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 output voltage (v oh ) to supply rail (v) load current (ma) ?40c +25c +85c +125c 10072-018 v sy = 15v figure 19. output voltage (v oh ) to supply rail vs. load current 0 50 100 150 200 250 300 350 400 450 ?50 ?25 0 25 50 75 100 125 output voltage (v ol ) to supply rail (mv) temperature (c) v sy = 15v r l = 2k ? r l = 10k ? r l = 100k ? 10072-019 figure 20. output voltage (v ol ) to supply rail vs. temperature
ada4638-1 data sheet rev. 0 | page 10 of 24 0 20 40 60 80 100 120 ?50 ?25 0 25 50 75 100 125 output voltage (v oh ) to supply rail (mv) temperature (c) r l = 2k ? r l = 10k ? r l = 100k ? 10072-017 v sy = 2.5v figure 21. output voltage (v oh ) to supply rail vs. temperature 0 0.2 0.4 0.6 0.8 1.0 1.2 024681012141618202224262830 supply current pe r amplifier (ma) supply voltage (v) ?40c +25c +85c +125c 10072-021 figure 22. supply current vs. supply voltage ?135 ?90 ?45 0 45 90 135 ?40 ?20 0 20 40 60 80 1k 10k 100k 1m 10m phase (degrees) gain (db) frequency (hz) 20pf 200pf gain phase v sy =2.5v r l = 10k ? 10072-022 figure 23. open-loop gain and phase vs. frequency 0 100 200 300 400 500 600 output voltage (v oh ) to supply rail (mv) ?50 ?25 0 25 50 75 100 125 temperature (c) r l = 2k ? r l = 10k ? r l = 100k ? v sy = 15v 10072-020 figure 24. output voltage (v oh ) to supply rail vs. temperature 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 ?50 ?25 0 25 50 75 100 125 supply current pe r amplifier (ma) temperature (c) v sy =15v v sy =2.5v v sy =5v 10072-024 figure 25. supply current vs. temperature ?135 ?90 ?45 0 45 90 135 ?40 ?20 0 20 40 60 80 1k 10k 100k 1m 10m phase (degrees) gain (db) frequency (hz) 20pf 200pf gain phase v sy =15v r l = 10k ? 10072-025 figure 26. open-loop gain and phase vs. frequency
data sheet ada4638-1 rev. 0 | page 11 of 24 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 10 100 1k 10k 100k 1m 10m closed-loop gain (db) frequency (hz) a v = +1 a v = +100 a v = +10 v sy =2.5v r l = 10k ? 10072-023 figure 27. closed-loop gain vs. frequency 0 20 40 60 80 100 120 100 1k 10k 100k 1m 10m cmrr (db) frequency (hz) v sy =2.5v v cm =v sy /2 10072-027 figure 28. cmrr vs. frequency ?20 0 20 40 60 80 100 120 140 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) psrr+ psrr? v sy =2.5v v cm =v sy /2 10072-028 figure 29. psrr vs. frequency ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 10 100 1k 10k 100k 1m 10m closed-loop gain (db) frequency (hz) a v = +1 a v = +100 a v = +10 v sy = 15v r l = 10k ? 10072-026 figure 30. closed-loop gain vs. frequency 0 20 40 60 80 100 120 100 1k 10k 100k 1m 10m cmrr (db) frequency (hz) v sy =15v v cm =v sy /2 10072-030 figure 31. cmrr vs. frequency ?20 0 20 40 60 80 100 120 140 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) psrr+ psrr? v sy =15v v cm =v sy /2 10072-031 figure 32. psrr vs. frequency
ada4638-1 data sheet rev. 0 | page 12 of 24 1m 0.01 0.1 1 10 100 1k 100 1k 10k 100k 1m 10m z out ( ? ) frequency (hz) a v = +1 a v = +100 a v = +10 10072-029 v sy =2.5v v cm =v sy /2 figure 33. closed-loop outp ut impedance vs. frequency voltage (0.5v/div) time (1s/div) v sy = 2.5v v in =1v p-p a v = +1 r l =10k ? c l =100pf 10072-033 figure 34. large signal transient response voltage (20mv/div) time (1s/div) 10072-034 v sy = 2.5v v in =100mv p-p a v = +1 r l =10k ? c l =100pf figure 35. small signal transient response 1m 0.01 0.1 1 10 100 1k 100 1k 10k 100k 1m 10m z out ( ? ) frequency (hz) a v = +1 a v = +100 a v = +10 10072-032 v sy = 15v v cm =v sy /2 figure 36. closed-loop outp ut impedance vs. frequency voltage (5v/div) time (10s/div) v sy =15v v in =24v p-p a v = +1 r l =10k ? c l =100pf 10072-036 figure 37. large signal transient response voltage (20mv/div) time (1s/div) 10072-037 v sy =15v v in =100mv p-p a v = +1 r l =10k ? c l =100pf figure 38. small signal transient response
data sheet ada4638-1 rev. 0 | page 13 of 24 0 10 20 30 40 50 60 70 80 1 10 100 1000 overshoot (%) load capacitance (pf) os+ os? 10072-035 v sy = 2.5v v in = 100mv p-p a v = +1 r l =10k ? figure 39. small signal overshoot vs. load capacitance ?1 0 1 2 3 ?0.2 ?0.1 0 0.1 output voltage (v) input voltage (v) time (10s/div) 10072-039 v sy =2.5v a v = ?100 v in =100mv p-p r l =10k ? c l =100pf figure 40. positive overload recovery ?3 ?2 ?1 0 1 ?0.1 0 0.1 0.2 output voltage (v) input voltage (v) time (10s/div) 10072-040 v sy = 2.5v a v = ?100 v in =100mv p-p r l =10k ? c l =100pf figure 41. negative overload recovery 0 10 20 30 40 50 60 70 80 1 10 100 1000 overshoot (%) load capacitance (pf) os+ os? 10072-038 v sy = 15v v in =100mv p-p a v = +1 r l =10k ? figure 42. small signal overshoot vs. load capacitance ?5 0 5 10 15 20 ?1.0 ?0.5 0 0.5 output voltage (v) input voltage (v) time (10s/div) 10072-042 v sy =15v a v = ?100 v in =500mv p-p r l =10k ? c l =100pf figure 43. positive overload recovery ?20 ?15 ?10 ?5 0 5 ?0.5 0 0.5 1.0 output voltage (v) input vol t age (v) time (10s/div) 10072-043 v sy = 15v a v = ?100 v in =500mv p-p r l =10k ? c l =100pf figure 44. negative overload recovery
ada4638-1 data sheet rev. 0 | page 14 of 24 10072-041 time (2s/div) voltage (1v/div) v sy = 2.5v a v = ?1 r l = 10k ? input output +5mv ?5mv error band post gain = 5 figure 45. positive settling time to 0.1% 10072-045 time (2s/div) voltage (1v/div) v sy = 2.5v a v = ?1 r l = 10k ? input output +5mv ?5mv error band post gain = 5 figure 46. negative settling time to 0.1% 1 10 100 1k 10k 100k voltage noise density (nv/ hz) frequency (hz) 10072-049 10 100 1k 10k v sy = 2.5v v cm = v sy /2 a v = +10 figure 47. voltage noise density vs. frequency 10072-044 time (2s/div) voltage (5v/div) v sy = 15v a v = ?1 r l = 10k ? input output +25mv ?25mv error band post gain = 5 figure 48. positive settling time to 0.1% 10072-048 time (2s/div) voltage (5v/div) v sy = 15v a v = ?1 r l = 10k ? input output +25mv ?25mv error band post gain = 5 figure 49. negative settling time to 0.1% 10 100 1k 10k 1 10 100 1k 10k 100k voltage noise density (nv/ hz) frequency (hz) v sy = 15v v cm = v sy /2 a v = +10 10072-046 figure 50. voltage noise density vs. frequency
data sheet ada4638-1 rev. 0 | page 15 of 24 voltage (0.2v/div) time (1s/div) v sy = 2.5v v cm =v sy /2 a v = +100 10072-047 figure 51. 0.1 hz to 10 hz noise 0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 1 thd + n (%) v in (v rms) v sy = 2.5v r l =10k ? f=1khz a v = +1 10072-051 80khz filter 500khz filter figure 52. thd + n vs. amplitude 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k thd + n (%) frequency (hz) 10072-052 v sy = 2.5v r l = 10k ? v in = 0.5v rms a v = +1 80khz filter 500khz filter figure 53. thd + n vs. frequency v sy = 15v v cm =v sy /2 a v = +100 10072-050 v o ltage (0.2v/div) time (1s/div) figure 54. 0.1 hz to 10 hz noise 0.001 0.01 0.1 1 10 100 0.001 0.01 0.1 10 1 thd + n (%) v in (v rms) v sy = 15v r l =10k ? f=1khz a v = +1 10072-053 80khz filter 500khz filter figure 55. thd + n vs. amplitude 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k thd + n (%) frequency (hz) 10072-054 v sy = 15v r l = 10k ? v in = 7v rms a v = +1 80khz filter 500khz filter figure 56. thd + n vs. frequency
ada4638-1 data sheet rev. 0 | page 16 of 24 applications information the ada4638-1 , with its wide supply voltage range of 4.5 v to 30 v, is a precision, rail-to-rail output, zero-drift operational amplifier that features a patented combination of auto-zeroing and chopping technique. this unique topology allows the ada4638-1 to maintain its low offset voltage over a wide tempera- ture range and over its operating lifetime. this amplifier offers ultralow input offset voltage of 4.5 v maximum and an input offset voltage drift of 80 nv/c maximum. offset voltage errors due to common-mode voltage swings and power supply varia- tions are also corrected by the auto-zeroing and chopping tech- nique, resulting in a superb typical cmrr figure of 142 db and a psrr figure of 143 db at a 15 v supply voltage. with ultrahigh dc accuracy and no 1/f noise component, the ada4638-1 is ideal for high gain amplification of low level signals in dc or low frequency applications without the risk of excessive output voltage errors. differentiation traditionally, zero-drift amplifiers are designed using either the auto-zeroing or chopping technique. each technique has its benefits and drawbacks. auto-zeroing usually results in low noise energy at the auto-zeroing frequency, at the expense of higher low frequency noise due to aliasing of wideband noise into the auto-zeroed frequency band. chopping results in lower low frequency noise at the expense of larger noise energy at the chopping frequency. the ada4638-1 uses both auto-zeroing and chopping in a patented ping-pong arrangement to obtain lower low frequency noise together with lower energy at the chopping and auto-zeroing frequencies, maximizing the signal- to-noise ratio for the majority of applications. the relatively high chopping frequency of 16 khz and auto-zeroing frequency of 8 khz simplifies filter requirements for a wide, useful bandwidth.
data sheet ada4638-1 rev. 0 | page 17 of 24 theory of operation figure 57 shows the ada4638-1 amplifier block diagram. the noninverting and inverting amplifier inputs are +in and Cin, respectively. the transconductance amplifiers, a1 and a2, are the two input gain stages; the a3 and a4 transconductance amplifiers are the nulling amplifiers used to correct the offsets of a1 and a2, and a out is the output amplifier. a four-phase cycle (1 to 4) controls the switches. in phase 1 (1), a1 is auto-zeroed where both the inputs of a1 are connected to +in. a1 produces a differential output current of v os1 gm1, where v os1 is the input offset voltage of a1, and gm1 is the differential transconductance of a1. the outputs of a1 are then connected to the inputs and outputs of a3. a3 is designed to have an equivalent resistance of 1/gm3, where gm3 is the transconduct- ance of a3. the amplified version of v os1 , which is v os1 gm1/gm3, is stored on capacitors c1 and c2. these capacitors, together with a3, are used to null out the offset of a1 when a1 amplifies the signal during the 3 and 4 phases. while a1 is being auto-zeroed, a2 (nulled by a4, c3, and c4) is used for signal amplification. the ada4638-1 differs from traditional auto-zero amplifiers in that the input offset voltage is also chopped during signal amplification. during 1, +in and ?in are applied to the noninverting and inverting inputs, respectively, of a2. however, during 2, both the inputs and outputs of a2 are inverted, and the input offset voltage of a2 is chopped. the combination of auto-zeroing and chopping offers two major benefits. first, any residual offset following the auto-zeroing process is reduced. during 1, the output offset voltage of a2 is +v osaz2 and during 2, it is Cv osaz2 , producing a theoretical average of zero. second, the aliased noise spectrum density at dc due to auto-zeroing is modulated up to the chopping frequency, and the prechopped noise spectrum density at the chopping frequency is modulated down to dc. this noise transformation lowers the noise spectrum density at dc, thus making zero-drift amplifiers ideal for low frequency signal amplification. during 3 and 4, the roles of a1 and a2 are reversed. a2 offset is nulled, and the input signal is chopped and amplified using a1. +in ?in a1 4 3 1 2 2 1 1 3 3 3 1 3 2 1 2 1 3 1 4 3 4 1 3 4 a2 a3 c1 c2 c3 c4 a out cc out a4 10072-157 figure 57. ada4638-1 amplifier block diagram input protection the ada4638-1 has internal esd protection diodes that are connected between the inputs and each supply rail. these diodes protect the input transistors in the event of electrostatic dis- charge and are reverse-biased during normal operation. however, if either input exceeds one of the supply rails, these esd diodes become forward-biased and large amounts of current begin to flow through them. without current limiting, this excessive fault current causes permanent damage to the device. if the inputs are expected to be subject to overvoltage conditions, insert a resistor in series with each input to limit the input current to 10 ma maximum. however, consider the resistor thermal noise effect on the entire circuit. no output phase reversal an undesired phenomenon, phase reversal (also known as phase inversion) occurs in many amplifiers when one or both of the inputs are driven beyond the specified input common-mode voltage range, in effect reversing the polarity of the output. in some cases, phase reversal can induce lockups and cause equipment damage as well as self destruction. the ada4638-1 has been carefully designed to prevent any output phase reversal, provided that both inputs are maintained within the supply voltages. if either one or both inputs may exceed either supply voltage, place resistors in series with the inputs to limit the current to less than 10 ma. the ada4638-1 features rail-to-rail output with a supply volt- age from 4.5 v to 30 v. figure 58 shows the input and output waveforms of the ada4638-1 configured as a unity-gain buffer with a supply voltage of 15 v and a resistive load of 10 k. the ada4638-1 does not exhibit phase reversal.
ada4638-1 data sheet rev. 0 | page 18 of 24 10072-158 time (2s/div) voltage (10v/div) v sy = 15v v out r l =10k ? v in figure 58. no phase reversal noise considerations 1/f noise 1/f noise, also known as pink noise or flicker noise, is inherent in semiconductor devices and increases as frequency decreases. at low frequency, 1/f noise is a major noise contributor and causes a significant output voltage offset when amplified by the noise gain of the circuit. however, the ada4638-1 eliminates the 1/f noise internally, thus making it an excellent choice for dc or low frequency high precision applications. the 0.1 hz to 10 hz voltage noise is only 1.2 v p-p at 15 v of supply voltage. the low frequency 1/f noise appears as a slow varying offset to the ada4638-1 and is greatly reduced by the combination of auto-zeroing and chopping technique. this allows the ada4638-1 to have a much lower noise at dc and low frequency in comparison to standard low noise amplifiers that are susceptible to 1/f noise. figure 47 and figure 50 show the voltage noise density of the ada4638-1 with no 1/f noise. comparator operation op amps are designed to operate in a closed-loop configuration with feedback from its output to its inverting input. figure 59 shows the ada4638-1 configured as a voltage follower with an input voltage, which is kept at midpoint of the power supplies. a1 and a2 indicate the placement of ammeters to measure supply currents. i sy + refers to the current flowing into the positive supply pin of the op amp, and i sy ? refers to the current flowing out of the negative supply pin of the op amp. from figure 60 , as expected in normal operating condition, the current flowing into the op amp is equivalent to the current flowing out of the op amp, where i sy + = i sy ?. ada4638-1 a1 100k ? 100k ? i sy + + v sy v out ?v sy i sy ? a2 10072-059 figure 59. voltage follower ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 5 10 15 20 25 30 i sy per amplifier (ma) v sy (v) i sy + i sy ? 10072-060 figure 60. supply current vs. supply voltage (voltage follower) in contrast to op amps, comparators are designed to work in an open-loop configuration and to drive logic circuits. although op amps are different from comparators, occasionally an unused section of a dual op amp is used as a comparator to save board space and cost; however, this is not recommended. figure 61 and figure 62 show the ada4638-1 configured as a comparator, with resistors r in1 and r in2 in series with the input pins. ada4638-1 a3 i total + a1 i sy + r in1 + v sy v out ?v sy i input + r in2 i input? a2 i sy ? a4 i total ? 10072-061 figure 61. comparator a
data sheet ada4638-1 rev. 0 | page 19 of 24 ada4638-1 a1 i total + a3 i sy + r in1 +v sy v out ?v sy i input + r in2 i input? a4 i sy ? a2 i total ? 10072-062 figure 62. comparator b figure 63 and figure 64 show the total supply current of the system, i total , and the actual currents, i sy , that flow into and out of the supply pins of the ada4638-1 . with r in1 = r in2 = 100 k and supply voltage of 30 v, the total supply current of the system is 800 a to 900 a. with smaller input series resistors, total supply current of the system increases much more. figure 65 and figure 66 show the supply currents with r in1 = r in2 = 0 . the total current of the system increases to 10 ma. i total = i sy + i input note that, at 30 v of supply voltage, 8 ma to 9 ma of current flows through the input pins. this is undesirable. the ada4638-1 is not recommended to be used as a comparator. if absolutely necessary, place resistors in series with the inputs of the ampli- fier to limit input current to less than 10 ma. for more details on op amps as comparators, refer to the an-849 application note , using op amps as comparators . ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 5 10 15 20 25 30 current (ma) v sy (v) i sy + i total ? i total + i sy ? 10072-063 figure 63. supply current vs. supply voltage (comparator a, r in1 = r in2 = 100 k) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 5 10 15 20 25 30 current (ma) v sy (v) i sy + i total ? i total + i sy ? 10072-064 figure 64. supply current vs. supply voltage (comparator b, r in1 = r in2 = 100 k) ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 0 5 10 15 20 25 30 current (ma) v sy (v) i sy + i total ? i total + i sy ? 10072-065 figure 65. supply current vs. supply voltage (comparator a, r in1 = r in2 = 0 k) ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 0 5 10 15 20 25 30 current (ma) v sy (v) i sy + i total ? i total + i sy ? 10072-066 figure 66. supply current vs. supply voltage (comparator b, r in1 = r in2 = 0 k)
ada4638-1 data sheet rev. 0 | page 20 of 24 precision low-side current shunt sensor many applications require the sensing of signals near the positive or negative rails. current shunt sensors are one such application and are mostly used for feedback control systems. they are also used in a variety of other applications, including power metering, battery fuel gauging and feedback controls in electrical power steering. in such application, it is desirable to use a shunt with very low resistance to minimize series voltage drop. this not only minimizes wasted power, but also allows the measurement of high currents while saving power. a typical shunt may be 100 m. at a measured current of 1 a, the voltage produced from the shunt is 100 mv, and the amplifier error sources are not critical. however, at low measured current in the 1 ma range, the 100 v generated across the shunt demands a very low offset voltage and drift amplifier to maintain absolute accuracy. the unique attributes of a zero- drift amplifier provides a solution. the ada4638-1 , with its input common-mode voltage that includes the lower supply rail, can be used for implementing low-side current shunt sensors. figure 67 shows a low-side current sensing circuit using the ada4638-1 . the ada4638-1 is configured as a difference amplifier with a gain of 1000. although the ada4638-1 has high common-mode rejection, the cmr of the system is limited by the external resistors. therefore, the key to high cmr for the system are resistors that are well matched from both the resistive ratio and relative drift, where r1/r2 = r3/r4. the resistors are important in determining the performance over manufacturing tolerances, time, and temperature. r2 100k? v sy v sy v out * *v out = amplifier gain voltage across r s = 1000 r s i = 100 i r l r s 0.1 ? r1 100 ? i ada4638-1 r4 100k ? r3 100 ? 10072-167 i figure 67. low-side current sensing circuit printed circuit board layout the ada4638-1 is a high precision device with ultralow offset voltage and offset voltage drift. therefore, care must be taken in the design of the printed circuit board (pcb) layout to achieve optimum performance of the ada4638-1 at board level. to avoid leakage currents, keep the surface of the board clean and free of moisture. coating the board surface creates a barrier to moisture accumulation and reduces parasitic resistance on the board. properly bypassing the power supplies and keeping the supply traces short minimizes power supply disturbances caused by output current variation. connect bypass capacitors as close as possible to the device supply pins. stray capacitances are a concern at the outputs and the inputs of the amplifier. it is recommended that signal traces be kept at a distance of at least 5 mm from supply lines to minimize coupling. a potential source of offset error is the seebeck voltage on the circuit board. the seebeck voltage occurs at the junction of two dissimilar metals and is a function of the temperature of the junction. the most common metallic junctions on a circuit board are solder-to-board trace and solder-to-component lead. figure 68 shows a cross section of a surface-mount component soldered to a pcb. a variation in temperature across the board (where t a1 t a2 ) causes a mismatch in the seebeck voltages at the solder joints thereby resulting in thermal voltage errors that degrade the performance of the ultralow offset voltage of the ada4638-1 . solder + + + + component lead copper trace v sc1 v ts1 t a1 surface-mount component pc board t a2 v sc2 v ts2 if t a1 t a2 , then v ts1 + v sc1 v ts2 + v sc2 10072-067 figure 68. mismatch in seebeck volt ages causes seebeck voltage error to minimize these thermocouple effects, orient resistors so that heat sources warm both ends equally. where possible, the input signal paths should contain matching numbers and types of components to match the number and type of thermocouple junctions. for example, dummy components, such as zero value resistors, can be used to match the thermoelectric error source (real resistors in the opposite input path). place matching compo- nents in close proximity and orient them in the same manner to ensure equal seebeck voltages, thus cancelling thermal errors. additionally, use leads that are of equal length to keep thermal conduction in equilibrium. keep heat sources on the pcb as far away from amplifier input circuitry as is practical. it is highly recommended to use a ground plane. a ground plane helps distribute heat throughout the board, maintains a constant temperature across the board, and reduces emi noise pickup.
data sheet ada4638-1 rev. 0 | page 21 of 24 outline dimensions 2.44 2.34 2.24 top view 8 1 5 4 0.30 0.25 0.20 bottom view pin 1 index area seating plane 0.80 0.75 0.70 1.70 1.60 1.50 0.203 ref 0.05 max 0.02 nom 0.50 bsc exposed pad 3.10 3.00 sq 2.90 p i n 1 i n d i c a t o r ( r 0 . 1 5 ) for proper connection of the exposed pad, refer to the pin configuration section of this data sheet. coplanarity 0.08 0.50 0.40 0.30 compliant to jedec standards mo-229-weed 01-24-2011-b figure 69. 8-lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp-8-11) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 70. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range package description package option branding ada4638-1acpz-r7 ?40c to +125c 8-lead lead frame chip scale package [lfcsp_wd] cp-8-11 a2w ada4638-1acpz-rl ?40c to +125c 8-lead lead frame chip scale package [lfcsp_wd] cp-8-11 a2w ada4638-1arz ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ada4638-1arz-r7 ?40c to +125c 8-lead standard small outline package [soic_n] r-8 ada4638-1arz-rl ?40c to +125c 8-lead standard small outline package [soic_n] r-8 1 z = rohs compliant part.
ada4638-1 data sheet rev. 0 | page 22 of 24 notes
data sheet ada4638-1 rev. 0 | page 23 of 24 notes
ada4638-1 data sheet rev. 0 | page 24 of 24 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10072-0-10/11(0)

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